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Skew-Tolerant Circuit Design
As advances in technology and circuit design boost operating frequencies of microprocessors, DSPs and other fast chips, new design challenges continue to emerge. One of the major performance limitations in today's chip designs is clock skew, the uncertainty in arrival times between a pair of clocks. Increasing clock frequencies are forcing many engineers to rethink their timing budgets and to use skew-tolerant circuit techniques for both domino and static circuits. While senior designers have long developed their own techniques for reducing the sequencing overhead of domino circuits, this knowledge has routinely been protected as trade secret and has rarely been shared. Skew-Tolerant Circuit Design presents a systematic way of achieving the same goal and puts it in the hands of all designers.
This book clearly presents skew-tolerant techniques and shows how they address the challenges of clocking, latching, and clock skew. It provides the practicing circuit designer with a clearly detailed tutorial and an insightful summary of the most recent literature on these critical clock skew issues.
CHAPTER 1 - SKEW-TOLERANT CIRCUIT DESIGN 1.1 Overhead in Flip-Flop Systems 1.2 Throughput and Latency Trends 1.2.1 Impact of Overhead on Throughput and Latency 1.2.2 Historical Trends 1.2.3 Future Predictions 1.2.4 Conclusions 1.3 Skew-Tolerant Static Circuits 1.4 Domino Circuits 1.4.1 Domino Gate Operation 1.4.2 Traditional Domino Clocking 1.4.3 Skew-Tolerant domino 1.5 Case Studies 1.5.1 Sequencing Overhead in a Static ASIC 1.5.2 Sequencing Overhead in the Alpha 21164 1.5.3 Timing Analysis with Clock Skew 1.6 A Look Ahead CHAPTER 2 - STATIC CIRCUITS 2.1 Preliminaries 2.1.1 Purpose of Memory Elements 2.1.2 Terminology 2.2 Static Memory Elements 2.2.1 Timing Diagrams 2.2.2 Sequencing Overhead 2.2.3 Time Borrowing 2.2.4 Min-Delay 2.3 Memory Element Design 2.3.1 Transparent Latches 2.3.2 Pulsed Latches 2.3.3 Flip-Flops 2.4 Historical Perspective 2.5 Summary CHAPTER 3 - DOMINO CIRCUITS 3.1 Skew-Tolerant Domino Timing 3.1.1 General Timing Constraints 3.1.2 Clock Domains 3.1.3 50% Duty Cycle 3.1.4 Single Gate per Phase 3.1.5 Min-Delay Constraints 3.1.6 Recommendations and Design Issues 3.2 Domino Gate Design 3.2.1 Monotonicity and Dual-Rail Domino 3.2.2 Footed and Unfooted Gates 3.2.3 Keeper Design 3.2.4 Robustness Issues 3.3 Historical Perspective 3.4 Summary CHAPTER 4 - CIRCUIT METHODOLOGY 4.1 Static/Domino Interface 4.1.1 Latch Placement 4.1.2 Static to Domino Interface 4.1.3 Domino to Static Interface 4.1.4 Timing Types 4.1.5 Qualified Clocks 4.1.6 Min-Delay Checks 4.2 Clocked Element Design 4.2.1 Latch Design 4.2.2 Domino Gate Design 4.2.3 Special Structures 4.3 Testability 4.3.1 Static Logic 4.3.2 Domino Logic 4.4 Historical Perspective 4.5 Summary CHAPTER 5 - CLOCKING 5.1 Clock Waveforms 5.1.1 Physical Clock Definitions 5.1.2 Clock Skew 5.1.3 Clock Domains 5.2 Skew-Tolerant Domino Clock Generation 5.2.1 Delay Line Clock Generators 5.2.2 Feedback Clock Generators 5.2.3 Putting It All Together 5.3 Summary CHAPTER 6 - TIMING ANALYSIS 6.1 Timing Analysis without Clock Skew 6.2 Timing Analysis with Clock Skew 6.2.1 Single Skew Formation 6.2.2 Exact Skew Formation 6.2.3 Clock Domain Formulation 6.2.4 Example 6.3 Extension to Flip-Flops and Domino Circuits 6.3.1 Flip-Flops 6.3.2 Domino Gates 6.4 Min-Delay 6.5 A Verification Algorithm 6.6 Results 6.7 Historical Perspective 6.8 Summary 6.8.1 Skewless Formulation 6.8.2 Single Skew Formulation 6.8.3 Exact Formulation 6.8.4 Clock Domain Formulation 6.9 Appendix: Timing Constraints CHAPTER 7 - CONCLUSIONS BIBLIOGRAPHY Series: The Morgan Kaufmann Series in Computer Architecture and Design